This disclosure relates to the field of data processing systems. More particularly, this disclosure relates to data processing systems including a translation buffer unit storing translation data to translate an input address of a memory address transaction to an output address and a translation control unit to provide translation data to the translation buffer unit.
It is known to provide data processing systems incorporating one or more translation buffer units that are supplied with translation data by a translation control unit. Such an arrangement may be used, for example, in the context of a system memory management unit of an integrated circuit including a plurality of transaction sources each generating virtual addresses which are then translated into physical addresses to access a shared memory.